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CY24272 rambus ? xdr? clock generator with zero sda hold time cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-42414 rev. *a revised february 17, 2011 rambus ? ? xdr? clock generator with zero sda hold time features meets rambus ? extended data rate (xdr?) clocking requirements 25 ps typical cycle-to-cycle jitter ? ?135 dbc/hz typical phase noise at 20 mhz offset 100 or 133 mhz differential clock input 300?667 mhz high speed clock support quad (open drain) differential output drivers supports frequency multipliers: 3, 4, 5, 6, 9/2 and 15/4 spread aware? 2.5 v operation 28-pin tssop package table 1. device comparison cy24271 CY24272 sda hold time = 300 ns (smbus compliant) sda hold time = 0 ns (i 2 c compliant) r rc = 200 ? typical (rambus standard drive) r rc = 295 ? minimum (reduced output drive) clk0 clk0b clk1 clk1b clk2 clk2b clk3 clk3b refclk,refclkb scl sda id0 id1 en rega en regb en regc en regd pll bypass mux /bypass en logic block diagram [+] feedback
CY24272 document number: 001-42414 rev. *a page 2 of 16 contents pinouts .............................................................................. 3 pll multiplier .................................................................... 4 input clock signal ............................................................ 4 modes of operation .......................................................... 4 device id and smbus device address ........................... 5 smbus protocol ................................................................ 5 smbus data byte definitions .......................................... 5 absolute maximum conditions ....................................... 7 dc operating conditions ................................................. 8 dc electrical specifications ............................................ 9 ac operating conditions ................................................. 9 ac electrical specification ............................................ 10 test and measurement setup ........................................ 11 example external resistor values and termination voltages for a 50 w channel ............ 11 signal waveforms .......................................................... 11 jitter ................................................................................. 11 ordering information ...................................................... 13 ordering code definitions ..... .................................... 13 package drawing and dimension ................................. 13 acronyms ........................................................................ 14 document conventions ................................................. 14 units of measure ....................................................... 14 document history page ................................................. 15 sales, solutions, and legal information ...................... 16 worldwide sales and design s upport ......... .............. 16 products .................................................................... 16 psoc solutions ......................................................... 16 [+] feedback
CY24272 document number: 001-42414 rev. *a page 3 of 16 pinouts figure 1. pin diagram - 28-pin tssop /bypass refclkb vdd clk0b vss clk2b clk3 clk3b vdd vss clk2 clk0 vss clk1 clk1b vdd vddp iset vssc sda id0 id1 en scl vssp vss refclk vddc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CY24272 table 2. pin defini tion - 28-pin tssop pin no. name io description 1 vddp pwr 2.5 v power supply for phased lock loop (pll) 2 vssp gnd ground 3 iset i set clock driver current (external resistor) 4 vss gnd ground 5 refclk i reference clock input (connect to clock source) 6 refclkb i complement of reference clock (connect to clock source) 7 vddc pwr 2.5 v power supply for core 8 vssc gnd ground 9 scl i smbus clock (connect to smbus) 10 sda i smbus data (connect to smbus) 11 en i output enable (cmos signal) 12 id0 i device id (cmos signal) 13 id1 i device id (cmos signal) 14 /bypass i refclk bypassing pll (cmos signal) 15 vdd pwr power supply for outputs 16 clk3b o complement clock output 17 clk3 o clock output 18 vss gnd ground 19 clk2b o complement clock output 20 clk2 o clock output 21 vss gnd ground 22 vdd pwr power supply for outputs 23 clk1b o complement clock output 24 clk1 o clock output 25 vss gnd ground 26 clk0b o complement clock output 27 clk0 o clock output 28 vdd pwr power supply for outputs [+] feedback
CY24272 document number: 001-42414 rev. *a page 4 of 16 pll multiplier ta b l e 3 shows the frequency multipliers in the pll, selectable by programming the smbus registers mult0, mult1, and mult2. default multiplier at power up is 4. input clock signal the xcg receives either a differ ential (refclk/ refclkb) or a single-ended reference clocking input (refclk). when the reference input clock is from a different clock source, it must meet the voltage levels and timing requirements listed in dc operating conditions on page 8 and ac operating conditions on page 9 . for a single-ended clock input, an external voltage divider and a supply voltage, as shown in figure 2 on page 7 , provide a reference voltage v th at the refclkb pin. this determines the proper trip point of refclk. for the range of v th specified in dc operating conditions on page 8 , the outputs also meet the dc and ac operating conditions tables. modes of operation the modes of operation are determined by the logic signals applied to the en a nd /bypass pins and the values in the five smbus registers: regtest, rega, regb, regc, and regd. table 5 on page 5 shows selection from one to all four of the outputs, the outputs disabled mode (en = low), and bypass mode (en = high, /bypass = low). there is an option reserved for vendor test. disabled outputs are set to high z. at power up, the smbus registers default to the last entry in table 6 on page 6 . the value at regtest is 0. the values at rega, regb, regc, and regd are all ?1?. thus, all outputs are controlled by the logic applied to en and /bypass. notes 1. output frequencies shown in tab l e 3 are based on nominal input frequencies of 100 mhz and 133.3 mhz. the pll multipliers are applicable to spread spectrum modulated input clock with maximum and mini mum input cycle time. the refsel bit in smbus 81h is set correctly as shown. 2. default pll multiplier at power up. table 3. pll multiplier selection register frequency multiplier output frequency (mhz) mult2 mult1 mult0 refclk = 100 mhz [1] , refsel = 0 refclk = 133 mhz [1] , refsel = 1 0 0 0 3 300 400 001 4 400 [2] ? 0 1 0 5 500 667 0 1 1 6 600 ? 1 0 0 reserved ? ? 1 0 1 9/2 450 600 1 1 0 reserved ? ? 1 1 1 15/4 375 500 table 4. smbus device addresses for CY24272 xcg hex address 8-bit smbus device address including operation device operation five most significant bits id1 id0 wr# / rd 0 write d8 110 11 00 0 read d9 1 1 write da 01 0 read db 1 2 write dc 10 0 read dd 1 3 write de 11 0 read df 1 [+] feedback
CY24272 document number: 001-42414 rev. *a page 5 of 16 device id and smbus device address the device id (id0 and id1) is a part of the smbus device 8-bit address. the least significant bi t of the address designates a write or read operation. table 4 on page 4 shows the addresses for four CY24272 devices on the same smbus. smbus protocol the CY24272 is a slave receiver supporting operations in the word and byte modes described in sections 5.5.4 and 5.5.5 of the smbus specification 2.0. dc specifications are modified to rambus standard to support 1.8, 2.5, and 3.3 volt devices . time out detection and packet error protocol smbus features are not supported. hold time for sda is reduced relative to the cy24271, so that it is compatible with i 2 c. smbus data byte definitions three data bytes are defined for the CY24272. byte 0 is for programming the pll multiplier registers and clock output registers. the definition of byte 2 is shown in table 6 on page 6 , table 7 on page 6 , and table 8 on page 6 . the upper five bits are the revision numbers of the device and the lower three bits are the id numbers assigned to the vendor by rambus. notes 3. bypass mode: refclk bypasses the pll to the output drivers. 4. default mode of operation is at power up. table 5. modes of operation for CY24272 en /bypass regtest rega regb regc regd clk0/clk0b clk1/clk1b clk2/clk2b clk3/clk3b l x x x x x x high z high z high z high z h x 1 x x x x reserved for vendor test h l 0 x x x x refclk/ refclkb [3] refclk/ refclkb refclk/ refclkb refclk/ refclkb h h 0 0 0 0 0 high z high z high z high z h h 0 0 0 0 1 high z high z high z clk/clkb h h 0 0 0 1 0 high z high z clk/clkb high z h h 0 0 0 1 1 high z high z clk/clkb clk/clkb h h 0 0 1 0 0 high z clk/clkb high z high z h h 0 0 1 0 1 high z clk/clkb high z clk/clkb h h 0 0 1 1 0 high z clk/clkb clk/clkb high z h h 0 0 1 1 1 high z clk/clkb clk/clkb clk/clkb h h 0 1 0 0 0 clk/clkb high z high z high z h h 0 1 0 0 1 clk/clkb high z high z clk/clkb h h 0 1 0 1 0 clk/clkb high z clk/clkb high z h h 0 1 0 1 1 clk/clkb high z clk/clkb clk/clkb h h 0 1 1 0 0 clk/clkb clk/clkb high z high z h h 0 1 1 0 1 clk/clkb clk/clkb high z clk/clkb h h 0 1 1 1 0 clk/clkb clk/clkb clk/clkb high z hh 0 [4] 1 [4] 1 [4] 1 [4] 1 [4] clk/clkb clk/clkb clk/clkb clk/clkb [+] feedback
CY24272 document number: 001-42414 rev. *a page 6 of 16 note 5. rw = read and write, ro = read only, pod = power on default. see table 3 on page 4 for pll multipliers and table 5 on page 5 for clock output selections. table 6. command code 80h [5] bit register pod type description 7 reserved 0 rw reserved (no internal function) 6 mult2 0 rw pll multiplier select (reference table 3 on page 4 ) 5mult1 0 rw 4mult0 1 rw 3 rega 1 rw clock 0 output select 2 regb 1 rw clock 1 output select 1 regc 1 rw clock 2 output select 0 regd 1 rw clock 3 output select table 7. command code 81h [5] bit register pod type description 7 reserved 0 rw reserved (no internal function) 6 reserved 0 rw 5 reserved 0 rw 4 reserved 0 rw 3 reserved 1 rw reserved (must be set to ?1? for proper operation) 2 refsel 0 rw reference frequency select (reference table 3 on page 4 ) 1 reserved 0 rw reserved (must be set to ?0? for proper operation) 0 regtest 0 rw reserved (must be set to ?0? for proper operation) table 8. command code 82h [5] bit register pod type description 7device revision number ? ro contact factory for device revision number information. 6?ro 5?ro 4?ro 3?ro 2 vendor id 0 ro rambus assigned vendor id code 11ro 00ro [+] feedback
CY24272 document number: 001-42414 rev. *a page 7 of 16 figure 2. differential and single-ended clock inputs absolute maximum conditions parameter description condition min max unit v dd clock buffer supply voltage ?0.5 4.6 v v ddc core supply voltage ?0.5 4.6 v v ddp pll supply voltage ?0.5 4.6 v v in input voltage (scl and sda) relative to v ss ?0.5 4.6 v input voltage (refclk/refclkb ) relative to v ss ?0.5 v dd + 1.0 v input voltage relative to v ss ?0.5 v dd + 0.5 v t s temperature, storage non-functional ?65 150 c t a temperature, operating ambient functional 0 70 c t j temperature, junction functional ? 150 c ? ja junction to ambient thermal resistance zero air flow ? 100 c/w esd hbm esd protection (human body model ) mil-std-883, method 3015 2000 ? v refclkb refclk input xdr clock generator input xdr clock generator refclk supply voltage v th differential input single-ended input [+] feedback
CY24272 document number: 001-42414 rev. *a page 8 of 16 dc operating conditions parameter description condition min max unit v ddp supply voltage for pll 2.5 v 5% 2.375 2.625 v v ddc supply voltage for core 2.5 v 5% 2.375 2.625 v v dd supply voltage for clock buffers 2.5 v 5% 2.375 2.625 v v ihclk input high voltage, refclk/refclkb 0.6 0.95 v v ilclk input low voltage, refclk/refclkb ?0.15 +0.15 v v ixclk [6] crossing point voltage, refclk/refclkb 200 550 mv ? v ixclk [6] difference in crossing point voltage, refclk/refclkb ? 150 mv v ih input signal high voltage at id0, id1, en, and /bypass 1.4 2.625 v v il input signal low voltage at id0, id1, en, and /bypass ?0.15 0.8 v v ih,sm input signal high voltage at scl and sda [7] 1.4 3.465 v v il,sm input signal low voltage at scl and sda ?0.15 0.8 v v th [8] input threshold voltage for single-ended refclk 0.35 0.5 v dd v v ih,se input signal high voltage for single-ended refclk v th + 0.3 2.625 v v il,se input signal low voltage for single-ended refclk ?0.15 v th ? 0.3 v t a ambient operating temperature 0 70 c notes 6. not 100% tested except v ixclk and ? v ixclk . parameters guaranteed by design and characte rizations, not 100% tested in production. 7. this range of scl and sda input high voltage enables the CY24272 for use with 3.3 v, 2.5 v, or 1.8 v smbus voltages. 8. single-ended operation guaranteed only when 0.8 < (v ih,se ? v th )/(v th ? v il , se ) < 1.2. [+] feedback
CY24272 document number: 001-42414 rev. *a page 9 of 16 ac operating conditions the ac operating conditions follow. [9] parameter description condition min max unit t cycle,in refclk, refclkb input cycle time refsel = 0, /bypass = high 9 11 ns refsel = 1, /bypass = high 7 8 ns /bypass = low 4 ? ns t jit,in(cc) input cycle to cycle jitter [10] ?185ps t dcin [11] input duty cycle over 10,000 cycles 40% 60% t cycle t rin / t fin rise and fall times measured at 20%?80% of input voltage for refclk and refclkb inputs 175 700 ps ? t rin / t fin rise and fall times difference ? 150 ps p min [12] modulation index for triangular modulation ? 0.6 % modulation index for non-triangular modulation ? 0.5 [13] % f min [12] input frequency modulation 30 33 khz t sr,in input slew rate (measured at 20%?80% of input voltage) for refclk 14v/ns c in,ref capacitance at refclk inputs ? 7 pf c in,cmos capacitance at cmos inputs ? 10 pf f scl smbus clock frequency input in scl pin dc 100 khz dc electrical specifications parameter description min typ max unit v ox [9] differential output crossing point voltage [14] ?1.08?v v cos [9] output voltage swing (peak-to-peak single-ended) [15] ?400?mv v ol,abs absolute output low voltage at clk[3:0], clk[3:0]b [16] 0.85 ? ? v v iset reference voltage for swing controlled current, i ref 0.98 1.0 1.02 v i dd [17] power supply current at 2.625v, f ref = 100 mhz, and f out = 300 mhz ? ? 85 ma i dd [17] power supply current at 2.625v, f ref = 133 mhz, and f out = 667 mhz ? ? 125 ma i ol/ i ref ratio of output low current to reference current [18] 6.8 7.0 7.2 i ol,abs minimum current at v ol,abs [19] 25 ? ? ma v ol,sda sda output low voltage at test conditio n of sda output low current = 4 ma ? ? 0.4 v i ol,sda sda output low voltage at test condition of sda voltage = 0.8 v 6 ? ? ma i oz current during high z per pin at clk[3:0], clk[3:0]b ? ? 10 ? a z out output dynamic impedance when cl ock output signal is at v ol = 0.9 v [20] 1000 ? ? ? notes 9. not 100% tested except v ixclk and ? v ixclk . parameters guaranteed by design and char acterizations, not 100% tested in production. 10. jitter measured at crossing points and is t he absolute value of the worst case deviation. 11. measured at crossing points. 12. if input modulation is used; input modulation is allowed but not required. 13. the amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew that cannot exceed the skew generated by the specified 0.6% triangular modulation. typically, the amount of allowed non-triangular modulation is about 0.5%. 14. v ox is measured on external divider network. 15. v cos = (clock output high voltage ? clock output low voltage), measured on the external divider network. 16. v ol_abs is measured at the clock output pins of the package. 17. this range of scl and sda input high voltage enables the CY24272 for use with 3.3 v, 2.5 v, or 1.8 v smbus voltages. 18. i ref is equal to v iset /r rc . 19. minimum i ol,abs is measured at the clock output pin with r rc = 266 ohms or less. 20. z out is defined at the output pins as (0.94 v ? 0.90 v)/(i 0.94 ? i 0.90 ) under conditions specified for i ol, abs . [+] feedback
CY24272 document number: 001-42414 rev. *a page 10 of 16 ac electrical specification the ac electrical specifications follow. [21] parameter description min typ max unit t cycle clock cycle time [22] 1.25 ? 3.34 ns t jit(cc) jitter over 1-6 clock cycles at 400?635 mhz [23] ?2540ps jitter over 1-6 clock cycles at 638?667 mhz ? 25 30 ps l 20 phase noise ssb spectral purity l(f) at 20 mhz offset: 400?500 mhz (in addition, device must not exceed l(f) = 10log[1+(5010 6 /f) 2.4 ] ?138 for f = 1 mhz to 100 mhz except for the region near f = refclk/q where q is the value of the internal reference divider.) ? ?135 ?128 dbc/hz t jit(hper,cc) cycle-to-cycle duty cycle error at 400?635 mhz ? 25 40 ps cycle-to-cycle duty cycle error at 636?667 mhz ? 25 30 ps ? t skew drift in t skew when ambient temperature varies between 0 c and 70 c and supply voltage varies between 2.375 v and 2.625 v. [24] ??15ps dc long term average out put duty cycle 45% 50 55% t cycle t eer,scc pll output phase error when tracking ssc ?100 ? 100 ps t cr ,t cf output rise and fall times at 400?667 mhz (measured at 20%?80% of output voltage) ?150? ps t cr,cf difference between output rise and fall times on the same pin of the single device (20%?80%) of 400?667 mhz [25] ? ? 100 ps table 9. smbus timing specification parameter description min max units fsmb smbus operating frequency 10 100 khz tbuf bus free time between stop and start condition 4.7 ? ? s thd:sta hold time after (repeated) start condition. after this period, the first clock is generated. 4.0 ? ? s tsu:sta repeated start condition setup time 4.7 ? ? s tsu:sto stop condition setup time 4.0 ? ? s thd:dat data hold time 0 ? ns tsu:dat data setup time 250 ? ns ttimeout detect clock lo w timeout ? ? not supported tlow clock low period 4.7 ? ? s thigh clock high period 4.0 50 ? s tlow:sext cumulative clock low extend time (slave device) ? 25 ms CY24272 doesn?t extend tlow:mext cumulative clock low extend time (master device) ? 10 ms tf clock/data fall time ? 300 ns tr clock/data rise time ? 1000 ns tpor time in which a device must be operational after power on reset ? 500 ms notes 21. not 100% tested except v ixclk and ? v ixclk . parameters guaranteed by design and characterizations, not 100% tested in production. 22. max and min output clock cycle times are based on nominal output s frequency of 300 and 667 mhz, respectively. for spread spe ctrum modulated differential or single-ended refclk, the output clock tracks the modulation of the input. 23. output short term jitter spec is the abso lute value of the worst case deviation. 24. t skew is the timing difference between any two of the four diff erential clocks and is measured at common mode voltage. ? t skew is the change in t skew when the operating temperature and supply voltage change. 25. t cr,cf applies only when appropriate r rc and output resistor network resistor values are selected to match pull up and pull down currents. [+] feedback
CY24272 document number: 001-42414 rev. *a page 11 of 16 test and measurement setup figure 3. clock outputs signal waveforms a physical signal that appears at the pins of a device is deemed valid or invalid depending on its voltage and timing relations with other signals. input and output voltage waveforms are defined as shown in figure 4 on page 12 . both rise and fall times are defined between the 20% and 80% points of the voltage swing, with the swing defined as v h ?v l . figure 5 on page 12 shows the definition of the output crossing point. the nominal crossing point between the complementary outputs is defined as the 50% po int of the dc voltage levels. there are two crossing points defined: vx+ at the rising edge of clk and vx? at the falling edge of clk. for some waveforms, both vx+ and vx? are below vx,nom (for example, if t cr is larger than t cf ). jitter this section defines the specific ations that relate to timing uncertainty (or jitter) of t he input and output waveforms. figure 6 on page 12 shows the definition of cycle-to-cycle jitter with respect to the falling edge of the clk signal. cycle-to-cycle jitter is the difference between cycle times of adjacent cycles. equal requirements apply rising edges of the clk signal. figure 7 on page 12 shows the definition of cycle-to-cycle duty cycle error (t dc,err ). cycle-to-cycle duty cycle is defined as the difference between t pw+ (high times) of adjacent differential clock cycles. equal requirements apply to t pw- , low times of the differential click cycles. differential driver clk clkb swing current control iset r rc measurement point v ts r 1 z ch v t r t1 c s r t2 r 3 r 2 measurement point v ts r 1 z ch v t r t1 c s r t2 r 3 r 2 example external resistor values and termination voltages for a 50 ? channel parameter value unit r 1 33.0 ? r 2 18.0 ? r 3 17.0 ? r t1 60.4 ? r t2 301 ? c s 2700 pf r rc 432 ? v ts 2.5 v v t 1.2 v [+] feedback
CY24272 document number: 001-42414 rev. *a page 12 of 16 figure 4. input and output waveforms figure 5. crossing point voltage figure 6. cycle-to-cycle jitter figure 7. cycle-to-cycle duty-cycle error v h t r t f 80% 20% v l v (t) vx.nom clk clkb vx+ vx- clk clkb t cycle,i t cycle,i+1 t j = t cycle,i - t cycle,i+1 over 10,000 consecutive cycles clk clkb t cycle, (i) t pw- (i) t pw+ (i) t pw- (i+1) t pw+ (i+1) t cycle, (i+1) t dc,err = t pw- (i) - t pw- (i+1) and t pw- (i+1) - t pw+ (i+1) [+] feedback
CY24272 document number: 001-42414 rev. *a page 13 of 16 package drawing and dimension figure 8. 28-pin thin shrunk small outline package (4.40-mm body) zz28 ordering information part number package type product flow pb-free CY24272zxc 28-pin tssop commercial, 0 c to 70 c CY24272zxct 28-pin tssop ? tape and reel commercial, 0 c to 70 c ordering code definitions t = tape and reel temperature range: c = commercial package type: zx = 28-pin tssop (pb-free) base device part number company id: cy = cypress cy 24272 zx c t 51-85120 *b [+] feedback
CY24272 document number: 001-42414 rev. *a page 14 of 16 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor esd electrostatic discharge pll phase locked loop tssop thin shrunk small outline package xdr extended data rate symbol unit of measure c degree celsius hz hertz khz kilo hertz mhz mega hertz s micro seconds a micro amperes ma milli amperes ms milli seconds ns nano seconds ? ohms % percent pf pico farads ps pico seconds mv milli volts vvolts wwatts [+] feedback
CY24272 document number: 001-42414 rev. *a page 15 of 16 document history page document title: CY24272 rambus ? xdr? clock generator with zero sda hold time document number: 001-42414 rev. ecn no. issue date orig. of change description of change ** 1749003 see ecn kvm/aesa new data sheet no 8 or 15/2 multipliers or 133mhz * 4 option max frequency is 667mhz *a 3175899 02/17/2 011 bash added ordering code definitions . updated package drawing and dimension . added acronyms and units of measure . updated in new template. [+] feedback
document number: 001-42414 rev. *a revised february 17, 2011 page 16 of 16 rambus is a registered trademark, and xdr is a trademark, of rambus inc . all products and company names mentioned in this document may be the trademarks of their respective holders. CY24272 ? cypress semiconductor corporation, 2007-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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